The invention relates to an electronic apparatus comprising
a plurality of stations; PA1 a bus interconnecting the stations for exchange of a message satisfying a signal protocol, the message containing successively time division multiplexed a header signal, a content signal and a signal indicating completion of the message, the bus comprising a first and second section; and PA1 a bridge station interconnecting the first and second section.
The invention also relates to a bridge station for use in such an electronic apparatus.
Such an electronic apparatus is known from the commercially available 12C bus system described in the "Data Handbook IC20: 80C51-based 8-bit microcontrollers" issued by Philips Semiconductors in 1994, pages 1141-1159.
The 12C bus uses two signal conductors: a clocksignal conductor (SCL) carrying a clocksignal and a datasignal conductor (SDA) carrying a datasignal. The bus may consist of one section containing a clocksignal conductor and a datasignal conductor, or of several sections, each containing its own clocksignal conductor and datasignal conductor, the sections being interconnected by bridge circuits which pass the clocksignal and the datasignal between the sections. The known bridge stations serve mainly for extending the maximum length of the 12C bus.
Message transfer via the 12C bus requires the stations to participate in various operations according to a signal protocol. When a station wants to initiate a message transfer it has to determine first of all whether the bus is free, which, according to the signal protocol, is the case if no other message transfer has started or if all message transfers that have been started earlier have been terminated by so-called "stop-conditions". These which involve a logic level transition in the datasignai when the clocksignal is at a level that indicates valid data. When the bus is free a station can begin transmitting. In this case all other stations have to monitor the bus for the transmission of so-called "start-conditions" (which also involve a logic level transition in the datasignal when the clocksignal is at a level that indicates valid data) and an address transmitted at a predetermined position after the such a start condition to determine whether they are called upon to participate in message transfer.
This imposes a speed limit on transmission via the 12C bus. If transmission speed were so fast that any one station were too slow to be able to monitor the transmission, errors may ensue because such a station might miss a start or stop condition, or detect a start or stop condition erroneously, leading it to attempt transmission or refrain from transmission erroneously.
Many integrated circuits are available that can function up to a certain speed as stations attached to an 12C bus. In principle it is possible to design additional integrated circuits that can transfer messages at a higher speed than these integrated circuits, but no use can be made of the higher speed of such additional circuits when they are combined with the existing integrated circuits on a conventional 12C bus. This is because errors due to missed or false start and stop conditions may ensue in a slow station during higher speed transfer even if the stations actually participating in transfer of a particular message were capable of transferring that particular message at the higher speed.